Course Outcomes
Combinational Networks
Ability to design, minimize, and analyze a combinational network.
Sequential Networks
Ability to design and analyze a sequential network.
Debug
Ability to test and verify a digital system that includes I/O, state machines and combinational networks.
HDL Design
Ability to design combinational and sequential circuits using a modern hardware description language (HDL).
Design Tools
Ability to use modern synthesis and technology mapping tools to implement digital circuits on an FPGA.